1. Field of the Invention
This invention is related to a memory, and particularly to a control circuit of SRAM and an operating method thereof.
2. Description of the Prior Art
According to the operating type, conventional memory can be divided into several categories, such as the dynamic random access memory (DRAM) and static random access memory (SRAM). Wherein, the memory cell of static random access memory (SRAM) is composed of a plurality of transistors, which have a high switching speed and do not need any additional upgrading circuit. The so-called “static state” is when the power is applied to the static random access memory and the stored data can be kept constant. On the contrary, the data stored in dynamic random access memory (DRAM) has to be upgraded periodically. However, when the power supply is stopped completely, the data stored in static random access memory will disappear.
The static random access memory (SRAM) is generally applied to the products, such as portable electronic devices, the System-on-Chip (SOC), etc. At present, the design of common static random access memory (SRAM) comprises various types of structure, such as five-transistor structure, six-transistor structure or eight-transistor structure, etc.
However, under advanced semiconductor processes, the write ability of static random access memory is relatively low, it is necessary to use more transistors to complete the memory cells of a bit, so that the unit capacity will be lower, and the power consumption will be higher. Therefore, although word-line boost circuits are used, it's the risk is that the gate oxidization layer will be easy to penetrate.
Therefore, in order to produce more efficient static random access memory, provide better operating efficiency and lower manufacturing cost, it is necessary to research and develop new auxiliary circuits for static random access memory.